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3.1.13
Offset Correction Value Registers (OFFCORR)
The offset correction value register is a read-only register which contains the most recent offset correction increment / decre-
ment value from the offset cancellation circuit. The value stored in this register indicate the amount of offset correction being ap-
plied to the SPI output data. The values has a resolution of 1 LSB.
Table 21. Offset Correction Value Register
Location
Bit
Address
$16
Register
OFFCORR
7
OFFCORR[7]
6
OFFCORR[6]
5
OFFCORR[5]
4
OFFCORR[4]
3
OFFCORR[3]
2
OFFCORR[2]
1
OFFCORR[1]
0
OFFCORR[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.14
Reserved Registers (Reserved)
Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and
performance.
Table 22. Reserved Registers
Location
Bit
Address
$1C
$1D
Register
Reserved
Reserved
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
Reset Value
0
0
0
0
0
0
0
0
3.2
3.2.1
Customer Accessible Data Array CRC Verification
OTP Shadow Register Array CRC Verification
The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of
g(x) = X 3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.
3.2.2
Writable Register CRC Verification
The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when
the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X 3 + X + 1, with a
seed value = ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.
MMA655x
Sensor
20
Freescale Semiconductor, Inc.
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